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priority, and will never be OR'ed with other alternate functions. The reader is referred to the pin map
section of the device datasheet for more information on the possible locations of each alternate function
and any priority settings.
28.3.2.1 Serial Wire Debug Port Connection
The SW Debug Port is routed as an alternate function and the SWDIO and SWCLK pin connections are
enabled by default with internal pull down resistors. It is possible to disable these pin connections (and
disable the pull down resistors) by setting the SWDIOPEN and SWCLKPEN bits in GPIO_ROUTE to 0.
WARNING: When the debug pins are disabled, the device can no longer be accessed by a debugger. A
reset will set the debug pins back to their default state as enabled. If you do disable the debug pins, make
sure you have at least a 3 second timeout at the start of your program code before you disable the debug
pins. This way the debugger will have time to halt the device after a reset before the pins are disabled.
The Serial Wire Viewer Output pin (SWO) can be enabled by setting the SWOPEN bit in GPIO_ROUTE.
This bit can also be routed to alternate locations by configuring the LOCATION bitfield in GPIO_ROUTE.
28.3.2.2 Analog Connections
When using the GPIO pin for analog functionality, it is recommended to disable the digital output and
set the MODEn in GPIO_Px_MODEL/GPIO_Px_MODEH equal to 0b0000 to disable the input sense
and pull resistors.
28.3.3 Interrupt Generation
The GPIO can generate an interrupt from the input of any GPIO pin on a device. The interrupts have
asynchronous sense capability, enabling wake-up from energy modes as low as EM3, see Figure 28.5 (p.
397) .
Figure 28.5. Pin n Interrupt Generation
EXTIPSELn[ 2:0]
EXTIRISE[ n]
IFS[ n]
IFC[ n]
IEN[ n]
PAn
PBn
wakeup
PCn
PDn
Synch
set clear
IF[ n]
IRQ_GPIO_EVEN/
IRQ_GPIO_ODD
PEn
PFn
Odd/even inputs
EXTIFALL[ n]
PRS
All pins with the same pin number (n) are grouped together to trigger one interrupt flag (EXT[n] in
GPIO_IF). The EXTIPSELn[2:0] bits in GPIO_EXTIPSELL or GPIO_EXTIPSELH select which port will
trigger the interrupt flag. The GPIO_EXTIRISE[n] and GPIO_EXTIFALL[n] registers enables sensing of
rising and falling edges. By setting the EXT[n] bit in GPIO_IEN, a high interrupt flag n, will trigger one
of two interrupt lines. The even interrupt line is triggered by any enabled even numbered interrupt flag,
while the odd is triggered by odd flags. The interrupt flags can be set and cleared by software by writing
the GPIO_IFS and GPIO_IFC registers, see Example 28.1 (p. 397) . Since the external interrupts
are asynchronous, they are sensitive to noise. To increase noise tolerance, the MODEL and MODEH
fields in the GPIO_Px_MODEL and GPIO_Px_MODEH registers, respectively, should be set to include
filtering for pins that have external interrupts enabled.
Example 28.1. Interrupt Example
Setting EXTIPSEL3 in GPIO_EXTIPSELL to 2 (Port C) and setting the GPIO_EXTIRISE[3] bit, the
interrupt flag EXT[3] in GPIO_IF will be triggered by a rising edge on pin 3 on PORT C. If EXT[3] in
GPIO_IEN is set as well, a interrupt request will be sent on IRQ_GPIO_ODD.
2011-04-12 - d0001_Rev1.10
397
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